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Adversarial Deepfakes: Evaluating Vulnerability of Deepfake Detectors to Adversarial Examples · Sleeping Coordination for Comprehensive Sensing Using Isotonic Regression and Domatic Partitions · (Bio)-behavioral CAD · N-version temperature-aware scheduling and binding · Noninvasive leakage power tomography of integrated circuits by compressive sensing · Nonparametric Combinatorial Regression for Shape Constrained Modeling · Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps · On the Application of Binary Neural Networks in Oblivious Inference · On-line fault detection of sensor measurements · P3: Privacy Preserving Positioning for Smart Automotive Systems · Peeking Into the Black Box: A Tutorial on Automated Design Optimization and Parameter Search · Perform-ML: Performance Optimized Machine Learning by Platform and Content Aware Customization · Phase Change Memory Write Cost Minimization by Data Encoding · Multisketches: Practical Secure Sketches Using Off-the-Shelf Biometric Matching Algorithms · Physical Unclonable Functions and Applications: A Tutorial · Post-silicon Resource Binding Customization for Low Power · Post-silicon timing characterization by compressed sensing · Power and Timing Side Channels for PUFs and their Efficient Exploitation · PriSearch: Efficient Search on Private Data · Privacy Preserving Localization for Smart Automotive Systems

Other values: ; A Built-In-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators A Framework for Collaborative Learning in Secure High-Dimensional Space A Primer on Hardware Security: Models, Methods, and Metrics A Probabilistic Constructive Approach to Optimization Problems A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multi-core Embedded Systems A Survey of Hardware Trojan Taxonomy and Detection A Timing Channel Spyware for the CSMA/CA Protocol A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection A general framework for spatial correlation modeling in VLSI design A unified framework for multimodal submodular IC trojan detection AHEAD: Automated Framework for Hardware Accelerated Iterative Data Analysis AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning Acceleration ARM2GC: Succinct Garbled Processor for Secure Computation ASCAI: Adaptive Sampling for acquiring Compact AI Active Control and Digital Rights Management of Integrated Circuit IP Cores Active Hardware Metering for Intellectual Property Protection and Security AdaNS: Adaptive Non-Uniform Sampling for Automated Design of Compact DNNs Adversarial Reprogramming of Text Classification Neural Networks An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors Anti-Collusion Position Estimation in Wireless Sensor Networks AutoRank: Automated Rank Selection for Effective Neural Network Customization Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms Automated Synthesis of Optimized Circuits for Secure Computation Automated checkpointing for enabling intensive applications on energy harvesting devices BIST-PUF: Online, Hardware-based Evaluation of Physically Unclonable Circuit Identifiers Balancing Security and Utility in Medical Devices? Behavioral synthesis techniques for intellectual property protection BioChipWork: Reverse Engineering of Microfluidic Biochips CAD-based Security, Cryptography, and Digital Rights Management CAMsure: Secure Content-Addressable Memory for Approximate Search CLEANN: Accelerated Trojan Shield for Embedded Neural Networks COINN: Crypto/ML Codesign for Oblivious Inference via Neural Networks Can EDA Combat the Rise of Electronic Counterfeiting? CausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAs Challenges and Opportunities in Broadband and Wireless Communication Designs Challenging benchmark for location discovery in ad hoc networks Chameleon: A Hybrid Secure Computation Framework for Machine Learning Applications Chime: Checkpointing long computations on intermittently energized IoT devices ClockPUF: Physical Unclonable Functions based on Clock Networks Coding-based Energy Minimization for Phase Change Memory Combined Modeling and Side Channel Attacks on Strong PUFs Compacting privacy-preserving k-nearest neighbor search using logic synthesis Consistency-based characterization for IC Trojan detection Coverage Problems in Wireless Ad-Hoc Sensor Networks CryptoML: Secure Outsourcing of Big Data Machine Learning Applications CuRTAIL: ChaRacterizing and Thwarting AdversarIal Deep Learning Customizing Neural Networks for Efficient FPGA Implementation CyCAR{\textquoteright}2013: First international academic workshop on security, privacy and dependability for cybervehicles D2Cyber: A Design Automation Tool for Dependable Cybercars DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives DeLight: Adding Energy Dimension To Deep Neural Networks Deep Learning on Private Data Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning DeepAttest: An End-to-End Attestation Framework for Deep Neural Networks DeepFense: Online Accelerated Defense Against Adversarial Deep Learning DeepInspect: A Black-box Trojan Detection and Mitigation Framework for Deep Neural Networks DeepMarks: A Digital Fingerprinting Framework for Deep Neural Networks DeepMarks: A Secure Fingerprinting Framework for Digital Rights Management of Deep Learning Models DeepSecure: Scalable Provably-Secure Deep Learning DeepSigns: A Generic Watermarking Framework for IP Protection of Deep Learning Models DeepSigns: An End-to-End Watermarking Framework for Protecting the Ownership of Deep Neural Networks EDA for Secure and Dependable Cybercars: Challenges and Opportunities EPIC: Ending Piracy of Integrated Circuits Editorial Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things EncoDeep: Realizing Bit-Flexible Encoding for Deep Neural Networks Ending Piracy of Integrated Circuits Ensuring Data Integrity in Sensor-Based Networked Systems Error models for light sensors by statistical analysis of raw sensor measurements Error-Tolerant Multi-Modal Sensor Fusion Evolving EDA Beyond its E-Roots: An Overview Exposure In Wireless Sensor Networks: Theory And Practical Solutions Exposure in wireless Ad-Hoc sensor networks ExtDict: Extensible Dictionaries for Data- and Platform-Aware Large-Scale Learning Extended abstract: Circuit CAD tools as a security threat Extended abstract: Designer{\textquoteright}s hardware Trojan horse FASE: FPGA Acceleration of Secure Function Evaluation FPGA PUF using programmable delay lines FPGA Time-Bounded Unclonable Authentication FPGA-based True Random Number Generation using Circuit Metastability with Adaptive Feedback Control FPGA-oriented Security FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA Fault tolerance techniques for wireless ad hoc sensor networks Flexible ASICs: Shared Masking for Multiple Media Processors Flexible Transformations For Learning Big Data FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips GALU: A Genetic Algorithm Framework for Logic Unlocking. ACM Digital Threats: Research and Practice (DTRAP) GTX: The MARCO GSRC Technology Extrapolation System GarbledCPU: A MIPS Processor for Secure Computation in Hardware Gate Characterization Using Singular Value Decomposition: Foundations and Applications GenMatch: Secure DNA Compatibility Testing GenUnlock: An Automated Genetic Algorithm Framework forUnlocking Logic Encryption GeneCAI: Genetic Evolution for Acquiring Compact AI Global error-tolerant algorithms for location discovery in ad-hoc wireless Netoworks Going deeper than deep learning for massive data analytics under physical constraints Guest Editors{\textquoteright} Introduction: Confronting the Hardware Trustworthiness Problem HASHTAG: Hash Signatures for Online Detection of Fault-Injection Attacks on Deep Neural Networks Hardware Metering Hardware Metering: A Survey. Hardware Security: Preparing Students for the Next Design Frontiers Hardware Security: Threat Models and Metrics Hardware Trojan Horse Benchmark via Optimal Creation and Placement of Malicious Circuitry Heart-to-Heart (H2H): Authentication for Implanted Medical Devices [updated; see the erratum] Hierarchical hybrid power supply networks High-Performance Optimizations on Tiled Many-Core Embedded Systems: A Matrix Multiplication Case Study High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization How challenging is modeling of a data set? Hybrid Heterogeneous Energy Supply Networks Hybrid Spatial Modeling of Non-Stationary Process Variations HypoEnergy: Hybrid supercapacitor-battery power-supply optimization for Energy efficiency I Know Where You are: Proofs of Presence Resilient to Malicious Provers ILP-based Engineering Change Identification Of Integrated Circuits Idetic: A High-level Synthesis Approach for Enabling Long Computations on Transiently-powered ASICs Input Vector Control for Post-Silicon Leakage Current Minimization under Manufacturing Variations Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview Integrated circuit digital rights management techniques using physical level characterization Intellectual Property Metering Interacting Particle-based Model for Missing Data in Sensor Networks: Foundations and Applications Iterative error-tolerant location discovery in ad-hoc wireless sensor networks Large-Scale Privacy-Preserving Matching and Search LaserSPECks: Laser SPECtroscopic trace-gas sensor networks - sensor integration and applications Learning to Manage Combined Energy Supply Systems Lightweight Secure PUFs Location Discovery in Ad-hoc Wireless Sensor Networks LookNN: Neural Network with No Multiplication Low Power Coordination in Wireless Ad-hoc Networks Low-power Resource Binding by Postsilicon Customization MAXelerator: FPGA Accelerator for Privacy Preserving Multiply-Accumulate (MAC) on Cloud Servers MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation Markov chain-based models for missing and faulty data in MICA2 sensor motes MetaCores: Design and Optimization Techniques N-variant IC design: methodology and applications PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs ProFlip: Targeted Trojan Attack with Progressive Bit Flips. International Conference on Computer Vision (ICCV) Probabilistic Constructive Optimization Techniques Processor-Based Strong Physical Unclonable Functions with Aging-Based Response Tuning Processors for Mobile Applications Protecting bus-based hardware IP by secret sharing Provably Complete Hardware Trojan Detection Using Test Point Insertion Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management Provably secure obfuscation of diverse watermarks for sequential circuits Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder based Security RISE: An Automated Framework for Real-Time Intelligent Video Surveillance on FPGA Rapid FPGA Characterization using Clock Synthesis and Signal Sparsity ReBNet: Residual Binarized Neural Network ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs Real time emulations: foundation and applications Remote activation of ICs for piracy prevention and digital right management Robust Privacy-Preserving Fingerprint Authentication Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching Robust stable radiometric fingerprinting for wireless devices SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs SSketch: An Automated Framework for Streaming Sketch-based Analysis of Big Data on FPGA SVD-Based Ghost Circuitry Detection SWANN: Small-World Architecture for Fast Convergence of Neural Networks Safe Machine Learning and Defeating Adversarial Attacks Scalable Binary Neural Network applications in Oblivious Inference Security based on Physical Unclonability and Disorder Security of Microfluidic Biochip: Practical Attacks and Countermeasures SemiHD: Semi-Supervised Learning Using Hyperdimensional Computing Sensor Network Architecture Shielding and Securing Integrated Circuits with Sensors Slender PUF Protocol: A lightweight, robust, and secure authentication by substring matching SpecMark: A Spectral Watermarking Framework for IP Protection of Speech Recognition Systems Statistical modeling and recovery of intermittent sensor data streams Sub-linear Privacy-preserving Search with Untrusted Server and Semi-honest Parties Symbolic Debugging Scheme for Optimized Hardware and Software Symbolic debugging of embedded hardware and software System-Architectures for Sensor Networks Issues, Alternatives, and Directions Techniques for Design and Implementation of Secure Reconfigurable PUFs Techniques for Foundry Identification Techniques for Maintaining Connectivity Ad-hoc Networks Under Energy Constraints Testing Techniques for Hardware Security The Fusion of Secure Function Evaluation and Logic Synthesis The challenges of model objective selection and estimation for ad-hoc network data sets Things, Trouble, Trust: On Building Trust in IoT Systems Time-Bounded Authentication of FPGAs TinyDL: Just-In-Time Deep Learning Solution For Constrained Embedded Systems TinyGarble2: Smart, Efficient, and Scalable Yao{\textquoteright}s Garble Circuit TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits Toward Practical Secure Stable Matching Trojan Signatures in DNN Weights Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach Trustworthy Hardware Ultra-low Power Current-based PUF Universal Adversarial Perturbations for Speech Recognition Systems Watermarking Technique for Sensor Networks: Foundations and Applications WaveGuard: Understanding and Mitigating Audio Adversarial Examples Worst- and Best-Case Coverage in Sensor Networks XONN: XNOR-based Oblivious Deep Neural Network Inference

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