Difference between revisions of "Hussain2019fase"
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|abstract=<p>We present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing the well-known cryptographic protocol named Yao\’s Garbled Circuit (GC). SFE allows two parties to jointly compute a function on their private data and learn the output without revealing their inputs to each other. FASE is designed to allow cloud servers to provide secure services to a large number of clients in parallel while preserving the privacy of the data from both sides. Current SFE accelerators either target specific applications, and therefore are not amenable to generic use, or have low throughput due to inefficient management of resources. In this work, we present a pipelined architecture along with an efficient scheduling scheme to ensure optimal usage of the available resources. The scheme is built around a simulator of the hardware design that schedules the workload and assigns the most suitable task to the encryption cores at each cycle. This, coupled with optimal management of the read and write cycles of the Block RAM on FPGA, results in a minimum 2 orders of magnitude improvement in terms of throughput per core for the reported benchmarks compared to the most recent generic GC accelerator. Moreover, our encryption core requires 17\% less resource compared to the most recent secure GC realization.\ </p> | |abstract=<p>We present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing the well-known cryptographic protocol named Yao\’s Garbled Circuit (GC). SFE allows two parties to jointly compute a function on their private data and learn the output without revealing their inputs to each other. FASE is designed to allow cloud servers to provide secure services to a large number of clients in parallel while preserving the privacy of the data from both sides. Current SFE accelerators either target specific applications, and therefore are not amenable to generic use, or have low throughput due to inefficient management of resources. In this work, we present a pipelined architecture along with an efficient scheduling scheme to ensure optimal usage of the available resources. The scheme is built around a simulator of the hardware design that schedules the workload and assigns the most suitable task to the encryption cores at each cycle. This, coupled with optimal management of the read and write cycles of the Block RAM on FPGA, results in a minimum 2 orders of magnitude improvement in terms of throughput per core for the reported benchmarks compared to the most recent generic GC accelerator. Moreover, our encryption core requires 17\% less resource compared to the most recent secure GC realization.\ </p> | ||
|address=San Diego | |address=San Diego | ||
|month=4 | |||
|year=2019 | |||
|booktitle=Field-Programmable Custom Computing Machines (FCCM) | |booktitle=Field-Programmable Custom Computing Machines (FCCM) | ||
|title=FASE: FPGA Acceleration of Secure Function Evaluation | |title=FASE: FPGA Acceleration of Secure Function Evaluation | ||
|entry=inproceedings | |entry=inproceedings | ||
}} | }} | ||
Revision as of 04:45, 4 September 2021
| Hussain2019fase | |
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| entry | inproceedings |
| address | San Diego |
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| author | Siam U. Hussain and Farinaz Koushanfar |
| booktitle | Field-Programmable Custom Computing Machines (FCCM) |
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| month | 4 |
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| title | FASE: FPGA Acceleration of Secure Function Evaluation |
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| year | 2019 |
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Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093