Difference between revisions of "Rouhani2015"
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|keywords=Streaming model; Big data; Dense matrix; FPGA; Low-rank matrix; HW/SW co-design; Matrix sketching | |keywords=Streaming model; Big data; Dense matrix; FPGA; Low-rank matrix; HW/SW co-design; Matrix sketching | ||
|abstract=<p>This paper proposes SSketch, a novel automated computing framework for FPGA-based online analysis of big data with dense (non-sparse) correlation matrices. SSketch targets streaming applications where each data sample can be processed only once and storage is severely limited. The stream of input data is used by SSketch for adaptive learning and updating a corresponding ensemble of lower dimensional data structures, a.k.a., a sketch matrix. A new sketching methodology is introduced that tailors the problem of transforming the big data with dense correlations to an ensemble of lower dimensional subspaces such that it is suitable for hardware-based acceleration performed by reconfigurable hardware. The new method is scalable, while it significantly reduces costly memory interactions and enhances matrix computation performance by leveraging coarse-grained parallelism existing in the dataset. To facilitate automation, SSketch takes advantage of a HW/SW co-design approach: It provides an Application Programming Interface (API) that can be customized for rapid prototyping of an arbitrary matrixbased data analysis algorithm. Proof-of-concept evaluations on a variety of visual datasets with more than 11 million nonzeros demonstrates up to 200 folds speedup on our hardwareaccelerated realization of SSketch compared to a software-based deployment on a general purpose processor.</p> | |abstract=<p>This paper proposes SSketch, a novel automated computing framework for FPGA-based online analysis of big data with dense (non-sparse) correlation matrices. SSketch targets streaming applications where each data sample can be processed only once and storage is severely limited. The stream of input data is used by SSketch for adaptive learning and updating a corresponding ensemble of lower dimensional data structures, a.k.a., a sketch matrix. A new sketching methodology is introduced that tailors the problem of transforming the big data with dense correlations to an ensemble of lower dimensional subspaces such that it is suitable for hardware-based acceleration performed by reconfigurable hardware. The new method is scalable, while it significantly reduces costly memory interactions and enhances matrix computation performance by leveraging coarse-grained parallelism existing in the dataset. To facilitate automation, SSketch takes advantage of a HW/SW co-design approach: It provides an Application Programming Interface (API) that can be customized for rapid prototyping of an arbitrary matrixbased data analysis algorithm. Proof-of-concept evaluations on a variety of visual datasets with more than 11 million nonzeros demonstrates up to 200 folds speedup on our hardwareaccelerated realization of SSketch compared to a software-based deployment on a general purpose processor.</p> | ||
|month=5 | |||
|year=2015 | |||
|booktitle=23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) | |booktitle=23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) | ||
|title=SSketch: An Automated Framework for Streaming Sketch-based Analysis of Big Data on FPGA | |title=SSketch: An Automated Framework for Streaming Sketch-based Analysis of Big Data on FPGA | ||
|entry=inproceedings | |entry=inproceedings | ||
}} | }} | ||
Revision as of 04:42, 4 September 2021
| Rouhani2015 | |
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| author | B. Rouhani and E. Songhori and A. Mirhoseini and F. Koushanfar |
| booktitle | 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) |
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| month | 5 |
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| title | SSketch: An Automated Framework for Streaming Sketch-based Analysis of Big Data on FPGA |
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| year | 2015 |
| doi | 10.1109/FCCM.2015.56 |
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| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7160069 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093