Difference between revisions of "Hu2013"
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|doi=10.7873/DATE.2013.263 | |doi=10.7873/DATE.2013.263 | ||
|abstract=<p><span>Vulnerability of modern integrated circuits (ICs) to hardware Trojans has been increasing considerably due to the globalization of semiconductor design and fabrication processes. The large number of parts and decreased controllability and observability to complex ICs internals make it difficult to efficiently perform Trojan detection using typical structural tests like path latency and leakage power. In this paper, we present new accurate methods for Trojan detection that are based upon post-silicon multimodal thermal and power characterization techniques. Our approach first estimates the detailed post-silicon spatial power consumption using thermal maps of the IC, then applies 2DPCA to extract features of the spatial power consumption, and finally uses statistical tests against the features of authentic ICs to detect the Trojan. To characterize real-world ICs accurately, we perform our experiments in presence of 20\% \– 40\% CMOS process variation. Our results reveal that our new methodology can detect Trojans with 3\–4 orders of magnitude smaller power consumptions than the total power usage of the chip, while it scales very well because of the spatial view to the ICs internals by the thermal mapping.</span></p> | |abstract=<p><span>Vulnerability of modern integrated circuits (ICs) to hardware Trojans has been increasing considerably due to the globalization of semiconductor design and fabrication processes. The large number of parts and decreased controllability and observability to complex ICs internals make it difficult to efficiently perform Trojan detection using typical structural tests like path latency and leakage power. In this paper, we present new accurate methods for Trojan detection that are based upon post-silicon multimodal thermal and power characterization techniques. Our approach first estimates the detailed post-silicon spatial power consumption using thermal maps of the IC, then applies 2DPCA to extract features of the spatial power consumption, and finally uses statistical tests against the features of authentic ICs to detect the Trojan. To characterize real-world ICs accurately, we perform our experiments in presence of 20\% \– 40\% CMOS process variation. Our results reveal that our new methodology can detect Trojans with 3\–4 orders of magnitude smaller power consumptions than the total power usage of the chip, while it scales very well because of the spatial view to the ICs internals by the thermal mapping.</span></p> | ||
|month=3 | |||
|year=2013 | |||
|journal=Design, Automation \& Test in Europe (DATE) | |journal=Design, Automation \& Test in Europe (DATE) | ||
|title=High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization | |title=High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization | ||
|entry=conference | |entry=conference | ||
}} | }} | ||
Revision as of 03:40, 4 September 2021
| Hu2013 | |
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| author | Kangqiao Hu and Abdullah Nazma Nowroz and Sherief Reda and Farinaz Koushanfar |
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| journal | Design, Automation \& Test in Europe (DATE) |
| month | 3 |
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| title | High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization |
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| year | 2013 |
| doi | 10.7873/DATE.2013.263 |
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| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6513709 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093