Difference between revisions of "Majzoobi2011time"
From ACES
(Import from BibTeX) |
m (Import from BibTeX) |
||
| Line 5: | Line 5: | ||
|abstract=<p>This paper introduces a novel technique to authenticate and identify field programmable gate arrays (FPGAs). The technique uses the reconfigurability feature of FPGAs to perform self-characterization and extract the unique timing of the FPGA building blocks over the space of possible inputs. The characterization circuit is then exploited for constructing a physically unclonable function (PUF). The PUF can accept different forms of challenges including pulse width, digital binary and placement challenges. The responses from the PUF are only verifiable by entities with access to the unique timing signature. However, the authentic device is the only entity who can respond within a given time constraint. The constraint is set by the gap between the speed of PUF evaluation on authentic hardware and simulation of its behavior. A suite of authentication protocols is introduced based on the time-bounded mechanism. We ensure that the responses are robust to fluctuations in operational conditions such as temperature and voltage variations by employing: (i) a linear calibration mechanism that adjusts the clock frequency by a feedback from on-chip temperature and voltage sensor readings, (ii) a differential PUF structure with real-valued responses that cancels out the common impact of variations on delays. Security against various attacks is discussed and a proof-of-concept implementation of signature extraction and authentication are demonstrated on Xilinx Virtex 5 FPGAs.</p> | |abstract=<p>This paper introduces a novel technique to authenticate and identify field programmable gate arrays (FPGAs). The technique uses the reconfigurability feature of FPGAs to perform self-characterization and extract the unique timing of the FPGA building blocks over the space of possible inputs. The characterization circuit is then exploited for constructing a physically unclonable function (PUF). The PUF can accept different forms of challenges including pulse width, digital binary and placement challenges. The responses from the PUF are only verifiable by entities with access to the unique timing signature. However, the authentic device is the only entity who can respond within a given time constraint. The constraint is set by the gap between the speed of PUF evaluation on authentic hardware and simulation of its behavior. A suite of authentication protocols is introduced based on the time-bounded mechanism. We ensure that the responses are robust to fluctuations in operational conditions such as temperature and voltage variations by employing: (i) a linear calibration mechanism that adjusts the clock frequency by a feedback from on-chip temperature and voltage sensor readings, (ii) a differential PUF structure with real-valued responses that cancels out the common impact of variations on delays. Security against various attacks is discussed and a proof-of-concept implementation of signature extraction and authentication are demonstrated on Xilinx Virtex 5 FPGAs.</p> | ||
|pages=1123-1135 | |pages=1123-1135 | ||
|month=3 | |||
|year=2011 | |||
|volume=6 | |volume=6 | ||
|journal=IEEE Transactions on Information Forensics and Security (TIFS) | |journal=IEEE Transactions on Information Forensics and Security (TIFS) | ||
|title=Time-Bounded Authentication of FPGAs | |title=Time-Bounded Authentication of FPGAs | ||
|entry=article | |entry=article | ||
}} | }} | ||
Revision as of 04:38, 4 September 2021
| Majzoobi2011time | |
|---|---|
| entry | article |
| address | |
| annote | |
| author | Mehrdad Majzoobi and Farinaz Koushanfar |
| booktitle | |
| chapter | |
| edition | |
| editor | |
| howpublished | |
| institution | |
| journal | IEEE Transactions on Information Forensics and Security (TIFS) |
| month | 3 |
| note | |
| number | |
| organization | |
| pages | 1123-1135 |
| publisher | |
| school | |
| series | |
| title | Time-Bounded Authentication of FPGAs |
| type | |
| volume | 6 |
| year | 2011 |
| doi | |
| issn | |
| isbn | |
| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5737786 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093