Difference between revisions of "Songhori2016"
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|keywords=Garbled Circuit, Secure Function Evaluation | |keywords=Garbled Circuit, Secure Function Evaluation | ||
|abstract=<p>We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao\’s garbled circuit protocol in hardware. GarbledCPU provides three degrees of freedom for SFE which allow leveraging the trade-off between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.</p> | |abstract=<p>We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao\’s garbled circuit protocol in hardware. GarbledCPU provides three degrees of freedom for SFE which allow leveraging the trade-off between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.</p> | ||
|month=6 | |||
|year=2016 | |||
|booktitle=Design Automation Conference | |booktitle=Design Automation Conference | ||
|title=GarbledCPU: A MIPS Processor for Secure Computation in Hardware | |title=GarbledCPU: A MIPS Processor for Secure Computation in Hardware | ||
|entry=inproceedings | |entry=inproceedings | ||
}} | }} | ||
Revision as of 03:43, 4 September 2021
| Songhori2016 | |
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| author | Songhori, Ebrahim M. and Shaza Zeitouni and Ghada Dessouky and T. Schneider and Ahmad-Reza Sadeghi and Farinaz Koushanfar |
| booktitle | Design Automation Conference |
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| month | 6 |
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| title | GarbledCPU: A MIPS Processor for Secure Computation in Hardware |
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| year | 2016 |
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| url | dl.acm.org/citation.cfm?id=2898027 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093