Difference between revisions of "Songhori2015tinygarble"
From ACES
(Import from BibTeX) |
m (Import from BibTeX) |
||
| Line 5: | Line 5: | ||
|keywords=Garbled Circuit, Hardware Synthesis, Logic Design, Multiparty Computation, Secure Function Evaluation, Yao{\textquoteright}s protocol | |keywords=Garbled Circuit, Hardware Synthesis, Logic Design, Multiparty Computation, Secure Function Evaluation, Yao{\textquoteright}s protocol | ||
|abstract=<p>We introduce TinyGarble, a novel automated methodology based on powerful logic synthesis techniques for generating and optimizing compressed Boolean circuits used in secure computation, such as Yao\’s Garbled Circuit (GC) protocol. TinyGarble achieves an unprecedented level of compactness and scalability by using a sequential circuit description for GC. We introduce new libraries and transformations, such that our sequential circuits can be optimized and securely evaluated by interfacing with available garbling frameworks. The circuit compactness makes the memory footprint of the garbling operation fit in the processor cache, resulting in fewer cache misses and thereby less CPU cycles. Our proof-of-concept implementation of benchmark functions using TinyGarble demonstrates a high degree of compactness and scalability. We improve the results of existing automated tools for GC generation by orders of magnitude; for example, TinyGarble can compress the memory footprint required for 1024-bit multiplication by a factor of 4,172, while decreasing the number of non-XOR gates by 67\%. Moreover, with TinyGarble we are able to implement functions that have never been reported before, such as SHA-3. Finally, our sequential description enables us to design and realize a garbled processor, using the MIPS I instruction set, for private function evaluation. To the best of our knowledge, this is the first scalable emulation of a general purpose processor.</p> | |abstract=<p>We introduce TinyGarble, a novel automated methodology based on powerful logic synthesis techniques for generating and optimizing compressed Boolean circuits used in secure computation, such as Yao\’s Garbled Circuit (GC) protocol. TinyGarble achieves an unprecedented level of compactness and scalability by using a sequential circuit description for GC. We introduce new libraries and transformations, such that our sequential circuits can be optimized and securely evaluated by interfacing with available garbling frameworks. The circuit compactness makes the memory footprint of the garbling operation fit in the processor cache, resulting in fewer cache misses and thereby less CPU cycles. Our proof-of-concept implementation of benchmark functions using TinyGarble demonstrates a high degree of compactness and scalability. We improve the results of existing automated tools for GC generation by orders of magnitude; for example, TinyGarble can compress the memory footprint required for 1024-bit multiplication by a factor of 4,172, while decreasing the number of non-XOR gates by 67\%. Moreover, with TinyGarble we are able to implement functions that have never been reported before, such as SHA-3. Finally, our sequential description enables us to design and realize a garbled processor, using the MIPS I instruction set, for private function evaluation. To the best of our knowledge, this is the first scalable emulation of a general purpose processor.</p> | ||
|month=5 | |||
|year=2015 | |||
|booktitle=IEEE Symposium on Security and Privacy (S\&P)(14\% acceptance rate) | |booktitle=IEEE Symposium on Security and Privacy (S\&P)(14\% acceptance rate) | ||
|title=TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits | |title=TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits | ||
|entry=inproceedings | |entry=inproceedings | ||
}} | }} | ||
Revision as of 03:42, 4 September 2021
| Songhori2015tinygarble | |
|---|---|
| entry | inproceedings |
| address | |
| annote | |
| author | E. Songhori and Siam U. Hussain and Ahmad-Reza Sadeghi and T. Schneider and F. Koushanfar |
| booktitle | IEEE Symposium on Security and Privacy (S\&P)(14\% acceptance rate) |
| chapter | |
| edition | |
| editor | |
| howpublished | |
| institution | |
| journal | |
| month | 5 |
| note | |
| number | |
| organization | |
| pages | |
| publisher | |
| school | |
| series | |
| title | TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits |
| type | |
| volume | |
| year | 2015 |
| doi | 10.1109/SP.2015.32 |
| issn | |
| isbn | |
| url | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7163039 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093