Difference between revisions of "Maj todaes 2011"
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|keywords=High level synthesis, low power, postsilicon optimization, resource binding customization | |keywords=High level synthesis, low power, postsilicon optimization, resource binding customization | ||
|abstract=<p>In this paper, we propose the first method for post-silicon customization of resource binding for low power application specific integrated circuits (ASICs) design. We devise and implement a new synthesis framework that generates a diverse set of resource binding candidates where any one of the candidates could be selected post-silicon. Orthogonal arrays are used to construct multiple candidates with diversified resource usage patterns. We tune the resource usage to match the unique power characteristic of each IC by selecting the best binding candidate that minimizes the pertinent chip\’s power consumption. We show efficient methods for embedding multiple binding candidates inside one design. Experimental evaluations on benchmark circuits demonstrate the effectiveness and low overhead of the proposed methods. For example, our post-silicon tuning achieves an average of 10\% power savings on the benchmark circuits for variations present in 45nm technology. The power savings of post-silicon binding customization are expected to increase with scaling and miniaturization of CMOS feature sizes that inherently incur higher variations.</p> | |abstract=<p>In this paper, we propose the first method for post-silicon customization of resource binding for low power application specific integrated circuits (ASICs) design. We devise and implement a new synthesis framework that generates a diverse set of resource binding candidates where any one of the candidates could be selected post-silicon. Orthogonal arrays are used to construct multiple candidates with diversified resource usage patterns. We tune the resource usage to match the unique power characteristic of each IC by selecting the best binding candidate that minimizes the pertinent chip\’s power consumption. We show efficient methods for embedding multiple binding candidates inside one design. Experimental evaluations on benchmark circuits demonstrate the effectiveness and low overhead of the proposed methods. For example, our post-silicon tuning achieves an average of 10\% power savings on the benchmark circuits for variations present in 45nm technology. The power savings of post-silicon binding customization are expected to increase with scaling and miniaturization of CMOS feature sizes that inherently incur higher variations.</p> | ||
|month=3 | |||
|year=2013 | |||
|number=in press | |number=in press | ||
|journal=ACM Transactions on Design Automation of Electronic Systems (TODAES) | |journal=ACM Transactions on Design Automation of Electronic Systems (TODAES) | ||
|title=Post-silicon Resource Binding Customization for Low Power | |title=Post-silicon Resource Binding Customization for Low Power | ||
|entry=article | |entry=article | ||
}} | }} | ||
Revision as of 03:39, 4 September 2021
| Maj todaes 2011 | |
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| author | Mehrdad Majzoobi and Farinaz Koushanfar |
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| journal | ACM Transactions on Design Automation of Electronic Systems (TODAES) |
| month | 3 |
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| number | in press |
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| title | Post-silicon Resource Binding Customization for Low Power |
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| year | 2013 |
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| url | http://dl.acm.org/citation.cfm?id=2442097 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093