Difference between revisions of "Majzoobi2011fpga"
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|url=http://dl.acm.org/citation.cfm?id=2044931 | |url=http://dl.acm.org/citation.cfm?id=2044931 | ||
|abstract=<p><span style="color: rgb(0, 0, 0); font-family: Verdana, Arial, Helvetica, sans-serif; font-size: 12.8px;">The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effectiveness of our approach.</span></p> | |abstract=<p><span style="color: rgb(0, 0, 0); font-family: Verdana, Arial, Helvetica, sans-serif; font-size: 12.8px;">The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effectiveness of our approach.</span></p> | ||
|month=10 | |||
|year=2011 | |||
|journal=Workshop on Cryptographic Hardware and Embedded Systems (CHES) | |journal=Workshop on Cryptographic Hardware and Embedded Systems (CHES) | ||
|title=FPGA-based True Random Number Generation using Circuit Metastability with Adaptive Feedback Control | |title=FPGA-based True Random Number Generation using Circuit Metastability with Adaptive Feedback Control | ||
|entry=conference | |entry=conference | ||
}} | }} | ||
Revision as of 03:39, 4 September 2021
| Majzoobi2011fpga | |
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| author | Mehrdad Majzoobi and Farinaz Koushanfar and Srini Devadas |
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| journal | Workshop on Cryptographic Hardware and Embedded Systems (CHES) |
| month | 10 |
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| title | FPGA-based True Random Number Generation using Circuit Metastability with Adaptive Feedback Control |
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| year | 2011 |
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| url | http://dl.acm.org/citation.cfm?id=2044931 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093