Difference between revisions of "Chung2015"
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|keywords=3D microprocessor, last-level cache, leakage energy optimization, narrow-width value, process variation, yield | |keywords=3D microprocessor, last-level cache, leakage energy optimization, narrow-width value, process variation, yield | ||
|abstract=<p>As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., die-stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrow-width values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.</p> | |abstract=<p>As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., die-stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrow-width values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy-efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.</p> | ||
|month=8 | |||
|year=2015 | |||
|volume=64 | |volume=64 | ||
|journal=IEEE Transactions on Computers | |journal=IEEE Transactions on Computers | ||
|title=An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors | |title=An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors | ||
|entry=article | |entry=article | ||
| | |pdf=Chung2015.pdf | ||
}} | }} | ||
Latest revision as of 17:34, 9 November 2021
| Chung2015 | |
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| entry | article |
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| author | S. Chung and J. Kong and F. Koushanfar |
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| journal | IEEE Transactions on Computers |
| month | 8 |
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| title | An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors |
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| volume | 64 |
| year | 2015 |
| doi | 10.1109/TC.2014.2378291 |
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| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977972 |
| Chung2015.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093