Difference between revisions of "Mirhoseini2015phase"
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|keywords=Encoding, memory management, optimization, phase change memory | |keywords=Encoding, memory management, optimization, phase change memory | ||
|abstract=<p>Phase change memory (PCM) is a promising next generation nonvolatile memory. Despite the currently popular charge-based storage techniques, PCM leverages a much more scalable thermal-resistive mechanism that enables sub-10 nm feature sizes. To realize PCM\&$\#$39;s potential, there are a number of technical challenges that need to be addressed, including limited wear endurance and high energy consumption of bit writes. Our work introduces a novel set of tools and methodologies for encoding data on PCM that optimizes its write performance. We develop a framework which exploits asymmetries in PCM read/write. We show that this coding problem is NP-complete. To provide a tractable solution, we propose two different methods: the first uses integer linear programming, and the second leverages dynamic programming to find an approximation of the optimal solution. Our methods target both single and multi-level cell PCM and can be directly applied to any asymmetric nonvolatile memory with bit-level accessibility. We further optimize our codes by leveraging data distributions. We devise a low-overhead architecture for the encoder module which can be easily integrated within the existing computer memory architecture. We demonstrate the applicability, low overhead, and efficiency of our proposed framework with extensive evaluations.</p> | |abstract=<p>Phase change memory (PCM) is a promising next generation nonvolatile memory. Despite the currently popular charge-based storage techniques, PCM leverages a much more scalable thermal-resistive mechanism that enables sub-10 nm feature sizes. To realize PCM\&$\#$39;s potential, there are a number of technical challenges that need to be addressed, including limited wear endurance and high energy consumption of bit writes. Our work introduces a novel set of tools and methodologies for encoding data on PCM that optimizes its write performance. We develop a framework which exploits asymmetries in PCM read/write. We show that this coding problem is NP-complete. To provide a tractable solution, we propose two different methods: the first uses integer linear programming, and the second leverages dynamic programming to find an approximation of the optimal solution. Our methods target both single and multi-level cell PCM and can be directly applied to any asymmetric nonvolatile memory with bit-level accessibility. We further optimize our codes by leveraging data distributions. We devise a low-overhead architecture for the encoder module which can be easily integrated within the existing computer memory architecture. We demonstrate the applicability, low overhead, and efficiency of our proposed framework with extensive evaluations.</p> | ||
|month=3 | |||
|year=2015 | |||
|volume=5 | |volume=5 | ||
|journal=IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Special Issue on Computing in Emerging Technologies | |journal=IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Special Issue on Computing in Emerging Technologies | ||
|title=Phase Change Memory Write Cost Minimization by Data Encoding | |title=Phase Change Memory Write Cost Minimization by Data Encoding | ||
|entry=article | |entry=article | ||
| | |pdf=Mirhoseini2015phase.pdf | ||
}} | }} | ||
Latest revision as of 17:37, 9 November 2021
| Mirhoseini2015phase | |
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| entry | article |
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| annote | |
| author | A. Mirhoseini and M. Potkonjak and F. Koushanfar |
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| chapter | |
| edition | |
| editor | |
| howpublished | |
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| journal | IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Special Issue on Computing in Emerging Technologies |
| month | 3 |
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| pages | |
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| title | Phase Change Memory Write Cost Minimization by Data Encoding |
| type | |
| volume | 5 |
| year | 2015 |
| doi | 10.1109/JETCAS.2015.2398211 |
| issn | |
| isbn | |
| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7048065 |
| Mirhoseini2015phase.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093