Difference between revisions of "Munir2014"
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|abstract=<p>With Moore\’s law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embedded systems exacerbates this design challenge and necessitates the architectural modeling of embedded systems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embedded systems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We verify our queueing theoretic modeling approach by running SPLASH-2 benchmarks on the SuperESCalar simulator (SESC). Results reveal that our queueing theoretic model qualitatively evaluates multi-core architectures accurately with an average difference of 5.6\% as compared to the architectures\’ evaluations from the SESC simulator. Our modeling approach can be used for performance per watt and performance per unit area characterizations of multi-core embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.</p> | |abstract=<p>With Moore\’s law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embedded systems exacerbates this design challenge and necessitates the architectural modeling of embedded systems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embedded systems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We verify our queueing theoretic modeling approach by running SPLASH-2 benchmarks on the SuperESCalar simulator (SESC). Results reveal that our queueing theoretic model qualitatively evaluates multi-core architectures accurately with an average difference of 5.6\% as compared to the architectures\’ evaluations from the SESC simulator. Our modeling approach can be used for performance per watt and performance per unit area characterizations of multi-core embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.</p> | ||
|pages=1872-1890 | |pages=1872-1890 | ||
|month=1 | |||
|year=2014 | |||
|number=1 | |number=1 | ||
|volume=74 | |volume=74 | ||
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|title=A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multi-core Embedded Systems | |title=A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multi-core Embedded Systems | ||
|entry=article | |entry=article | ||
| | |pdf=Munir2014.pdf | ||
}} | }} | ||
Latest revision as of 17:38, 9 November 2021
| Munir2014 | |
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| entry | article |
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| author | Arslan Munir and Ann Gordon-Ross and Sanjay Ranka and Farinaz Koushanfar |
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| howpublished | |
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| journal | Elsevier Journal of Parallel and Distributed Computing (JPDC) |
| month | 1 |
| note | |
| number | 1 |
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| pages | 1872-1890 |
| publisher | |
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| title | A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multi-core Embedded Systems |
| type | |
| volume | 74 |
| year | 2014 |
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| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6081397 |
| Munir2014.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093