Difference between revisions of "Wong2005"
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|abstract=ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micron manufacturability) trends favor FPGA as an implementation platform. In order to combine the advantages of both platforms and alleviate their disadvantages, recently a number of approaches, such as structured ASIC/regular fabrics, have been proposed. Our goal is to introduce an approach that has the same objective, but is orthogonal to those already proposed. The idea is to implement several ASIC designs in such a way that they share the datapath, memory structure, and several bottom layers of interconnect, while each design has only a few unique metal layers. We identified and addressed two main problems in our quest to develop a CAD flow for realization of such designs. They are: (i) the creation of the datapath, and (ii) the identification of common and unique interconnect for each design. Both problems are solved optimally using ILP formulations. We assembled a design flow platform using two new programs and the Trimaran and Shade tools. We quantitatively analyzed the advantages and disadvantages of the approach using the Mediabench benchmark suite. | |abstract=ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micron manufacturability) trends favor FPGA as an implementation platform. In order to combine the advantages of both platforms and alleviate their disadvantages, recently a number of approaches, such as structured ASIC/regular fabrics, have been proposed. Our goal is to introduce an approach that has the same objective, but is orthogonal to those already proposed. The idea is to implement several ASIC designs in such a way that they share the datapath, memory structure, and several bottom layers of interconnect, while each design has only a few unique metal layers. We identified and addressed two main problems in our quest to develop a CAD flow for realization of such designs. They are: (i) the creation of the datapath, and (ii) the identification of common and unique interconnect for each design. Both problems are solved optimally using ILP formulations. We assembled a design flow platform using two new programs and the Trimaran and Shade tools. We quantitatively analyzed the advantages and disadvantages of the approach using the Mediabench benchmark suite. | ||
|pages=909 - 914 | |pages=909 - 914 | ||
|month= | |||
|year=2005 | |||
|booktitle=ACM/IEEE-CAS/EDAC Design Automation Conference (DAC) | |booktitle=ACM/IEEE-CAS/EDAC Design Automation Conference (DAC) | ||
|title=Flexible ASICs: Shared Masking for Multiple Media Processors | |title=Flexible ASICs: Shared Masking for Multiple Media Processors | ||
|entry=inproceedings | |entry=inproceedings | ||
| | |pdf=Wong2005.pdf | ||
}} | }} | ||
Latest revision as of 17:40, 9 November 2021
| Wong2005 | |
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| entry | inproceedings |
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| author | J. Wong and F. Koushanfar and M. Potkonjak |
| booktitle | ACM/IEEE-CAS/EDAC Design Automation Conference (DAC) |
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| pages | 909 - 914 |
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| title | Flexible ASICs: Shared Masking for Multiple Media Processors |
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| year | 2005 |
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| Wong2005.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093