Difference between revisions of "Majzoobi2010fpga"
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|url=http://dl.acm.org/citation.cfm?id=1929305 | |url=http://dl.acm.org/citation.cfm?id=1929305 | ||
|abstract=<p>This paper introduces a novel technique for extracting the unique timing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and placement challenges can be built upon the delay signatures. We introduce a suite of new authentication protocols that take into account non-triviality of bitstream reverse-engineering in addition to the FPGA\’s unprecedented speed in responding to challenges. Our technique is secure against various attacks and robust to fluctuations in operational conditions. Proof of concept implementation of the signature extraction and evaluations of the proposed methods are demonstrated on Xilinx Virtex 5 FPGAs. Experimental results demonstrate practicality of the proposed techniques.</p> | |abstract=<p>This paper introduces a novel technique for extracting the unique timing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and placement challenges can be built upon the delay signatures. We introduce a suite of new authentication protocols that take into account non-triviality of bitstream reverse-engineering in addition to the FPGA\’s unprecedented speed in responding to challenges. Our technique is secure against various attacks and robust to fluctuations in operational conditions. Proof of concept implementation of the signature extraction and evaluations of the proposed methods are demonstrated on Xilinx Virtex 5 FPGAs. Experimental results demonstrate practicality of the proposed techniques.</p> | ||
|month=5 | |||
|year=2010 | |||
|series=Lecture Notes in Computer Science | |series=Lecture Notes in Computer Science | ||
|booktitle=Information Hiding | |booktitle=Information Hiding | ||
|title=FPGA Time-Bounded Unclonable Authentication | |title=FPGA Time-Bounded Unclonable Authentication | ||
|entry=inproceedings | |entry=inproceedings | ||
| | |pdf=Majzoobi2010fpga.pdf | ||
}} | }} | ||
Latest revision as of 17:37, 9 November 2021
| Majzoobi2010fpga | |
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| entry | inproceedings |
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| annote | |
| author | Mehrdad Majzoobi and Ahmed Elnably and Farinaz Koushanfar |
| booktitle | Information Hiding |
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| edition | |
| editor | Rainer B{\"o}hme and Philip Fong and Reihaneh {Safavi-Naini} |
| howpublished | |
| institution | |
| journal | |
| month | 5 |
| note | |
| number | |
| organization | |
| pages | |
| publisher | |
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| series | Lecture Notes in Computer Science |
| title | FPGA Time-Bounded Unclonable Authentication |
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| volume | |
| year | 2010 |
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| isbn | |
| url | http://dl.acm.org/citation.cfm?id=1929305 |
| Majzoobi2010fpga.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093