Difference between revisions of "Kong2013"
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|keywords=Circuit aging, Multi-core processor, Negative bias temperature instability, Physically unclonable function, Post-silicon tuning, Secure computing platform | |keywords=Circuit aging, Multi-core processor, Negative bias temperature instability, Physically unclonable function, Post-silicon tuning, Secure computing platform | ||
|abstract=<p><span>A strong physically unclonable function (PUF) is a circuit structure that extracts an exponential number of unique chip signatures from a bounded number of circuit components. The strong PUF unique signatures can enable a variety of low-overhead security and intellectual property protection protocols applicable to several computing platforms. This paper proposes a novel lightweight (low overhead) strong PUF based on the timings of a classic processor architecture. A small amount of circuitry is added to the processor for on-the-fly extraction of the unique timing signatures. To achieve desirable strong PUF properties, we develop an algorithm that leverages intentional post-silicon aging to tune the inter- and intra-chip signatures variation. Our evaluation results show that the new PUF meets the desirable inter- and intra-chip strong PUF characteristics, whereas its overhead is much lower than the existing strong PUFs. For the processors implemented in 45 nm technology, the average inter-chip Hamming distance for 32-bit responses is increased by 16.1\% after applying our post-silicon tuning method; the aging algorithm also decreases the average intra-chip Hamming distance by 98.1\% (for 32-bit responses).</span></p> | |abstract=<p><span>A strong physically unclonable function (PUF) is a circuit structure that extracts an exponential number of unique chip signatures from a bounded number of circuit components. The strong PUF unique signatures can enable a variety of low-overhead security and intellectual property protection protocols applicable to several computing platforms. This paper proposes a novel lightweight (low overhead) strong PUF based on the timings of a classic processor architecture. A small amount of circuitry is added to the processor for on-the-fly extraction of the unique timing signatures. To achieve desirable strong PUF properties, we develop an algorithm that leverages intentional post-silicon aging to tune the inter- and intra-chip signatures variation. Our evaluation results show that the new PUF meets the desirable inter- and intra-chip strong PUF characteristics, whereas its overhead is much lower than the existing strong PUFs. For the processors implemented in 45 nm technology, the average inter-chip Hamming distance for 32-bit responses is increased by 16.1\% after applying our post-silicon tuning method; the aging algorithm also decreases the average intra-chip Hamming distance by 98.1\% (for 32-bit responses).</span></p> | ||
|month=11 | |||
|year=2013 | |||
|volume=2 | |volume=2 | ||
|journal=IEEE Transactions on Emerging Topics in Computing | |journal=IEEE Transactions on Emerging Topics in Computing | ||
|title=Processor-Based Strong Physical Unclonable Functions with Aging-Based Response Tuning | |title=Processor-Based Strong Physical Unclonable Functions with Aging-Based Response Tuning | ||
|entry=article | |entry=article | ||
| | |pdf=Kong2013.pdf | ||
}} | }} | ||
Latest revision as of 17:35, 9 November 2021
| Kong2013 | |
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| entry | article |
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| author | Kong, Joonho and Farinaz Koushanfar |
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| journal | IEEE Transactions on Emerging Topics in Computing |
| month | 11 |
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| title | Processor-Based Strong Physical Unclonable Functions with Aging-Based Response Tuning |
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| volume | 2 |
| year | 2013 |
| doi | 10.1109/TETC.2013.2289385 |
| issn | |
| isbn | |
| url | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6656920 |
| Kong2013.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093