Difference between revisions of "Chung2015"

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|title=An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors
|title=An Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors
|entry=article
|entry=article
|pdf=Chung2015.pdf
}}
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Latest revision as of 18:34, 9 November 2021

Chung2015
entryarticle
address
annote
authorS. Chung and J. Kong and F. Koushanfar
booktitle
chapter
edition
editor
howpublished
institution
journalIEEE Transactions on Computers
month8
note
number
organization
pages
publisher
school
series
titleAn Energy-efficient Last-level Cache Architecture for Process Variation-tolerant 3D Microprocessors
type
volume64
year2015
doi10.1109/TC.2014.2378291
issn
isbn
urlhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977972
pdfChung2015.pdf

File:Chung2015.pdf

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Email:
farinaz@ucsd.edu
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Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
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Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093