Difference between revisions of "Yao2013"
From ACES
(Import from BibTeX) |
m (Import from BibTeX) |
||
| Line 4: | Line 4: | ||
|doi=10.7873/DATE.2013.095 | |doi=10.7873/DATE.2013.095 | ||
|abstract=<p><span>Physical Unclonable Functions (PUFs) extract unique chip signatures from process variations. They are used in identification, authentication, integrity verification, and anti-counterfeiting tasks. We introduce new PUF techniques that extract bits from pairwise skews between sinks of a clock network. These techniques inherit the stability of clock network, but require a return network to deliver clock pulses to a certain region, where they are compared. Our algorithms select equidistant sinks and route the return network, then derive chip-specific random bits from available data with a moderate overhead. SPICE-based evaluation of clock-PUFs using a 45nm CMOS technology validates the operability, stability, uniqueness, randomness, and their low overhead.</span></p> | |abstract=<p><span>Physical Unclonable Functions (PUFs) extract unique chip signatures from process variations. They are used in identification, authentication, integrity verification, and anti-counterfeiting tasks. We introduce new PUF techniques that extract bits from pairwise skews between sinks of a clock network. These techniques inherit the stability of clock network, but require a return network to deliver clock pulses to a certain region, where they are compared. Our algorithms select equidistant sinks and route the return network, then derive chip-specific random bits from available data with a moderate overhead. SPICE-based evaluation of clock-PUFs using a 45nm CMOS technology validates the operability, stability, uniqueness, randomness, and their low overhead.</span></p> | ||
|month=3 | |||
|year=2013 | |||
|booktitle=Design, Automation \& Test in Europe (DATE) | |booktitle=Design, Automation \& Test in Europe (DATE) | ||
|title=ClockPUF: Physical Unclonable Functions based on Clock Networks | |title=ClockPUF: Physical Unclonable Functions based on Clock Networks | ||
|entry=inproceedings | |entry=inproceedings | ||
}} | }} | ||
Revision as of 04:40, 4 September 2021
| Yao2013 | |
|---|---|
| entry | inproceedings |
| address | |
| annote | |
| author | Yida Yao and Myung-Bo Kim and Jianmin Li and Igor L. Markov and Farinaz Koushanfar |
| booktitle | Design, Automation \& Test in Europe (DATE) |
| chapter | |
| edition | |
| editor | |
| howpublished | |
| institution | |
| journal | |
| month | 3 |
| note | |
| number | |
| organization | |
| pages | |
| publisher | |
| school | |
| series | |
| title | ClockPUF: Physical Unclonable Functions based on Clock Networks |
| type | |
| volume | |
| year | 2013 |
| doi | 10.7873/DATE.2013.095 |
| issn | |
| isbn | |
| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6513541 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093