Difference between revisions of "Majzoobi2010"
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|keywords=FPGA majority voting physical unclonable functions programmable delay line tuning | |keywords=FPGA majority voting physical unclonable functions programmable delay line tuning | ||
|abstract=<p>This paper proposes a novel approach for efficient implementation of a real-valued arbiter-based physical unclonable function (PUF) on FPGA. We introduce a high resolution programmable delay logic (PDL) implemented by lookup table (LUT) internal structure. Using the PDL, we perform fine tuning to cancel out delay skews caused by asymmetries in routing and systematic variations. We devise a symmetric switch structure that can be easily implemented on FPGA. To mitigate the arbiter metastability problem, we present and analyze methods for majority voting of responses. Lastly, a method to classify and group challenges into different robustness sets is introduced, to further increase the corresponding responses\’ stability in the face of environmental variations. Experimental evaluations show that the responses to robust challenges have an average error rate of less than 2\% under temperature variations from -10oC to 75oC.</p> | |abstract=<p>This paper proposes a novel approach for efficient implementation of a real-valued arbiter-based physical unclonable function (PUF) on FPGA. We introduce a high resolution programmable delay logic (PDL) implemented by lookup table (LUT) internal structure. Using the PDL, we perform fine tuning to cancel out delay skews caused by asymmetries in routing and systematic variations. We devise a symmetric switch structure that can be easily implemented on FPGA. To mitigate the arbiter metastability problem, we present and analyze methods for majority voting of responses. Lastly, a method to classify and group challenges into different robustness sets is introduced, to further increase the corresponding responses\’ stability in the face of environmental variations. Experimental evaluations show that the responses to robust challenges have an average error rate of less than 2\% under temperature variations from -10oC to 75oC.</p> | ||
|month=12 | |||
|year=2010 | |||
|journal=IEEE Workshop on Information Forensics and Security | |journal=IEEE Workshop on Information Forensics and Security | ||
|title=FPGA PUF using programmable delay lines | |title=FPGA PUF using programmable delay lines | ||
|entry=conference | |entry=conference | ||
}} | }} | ||
Revision as of 03:35, 4 September 2021
| Majzoobi2010 | |
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| author | Mehrdad Majzoobi and Farinaz Koushanfar and Srini Devadas |
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| journal | IEEE Workshop on Information Forensics and Security |
| month | 12 |
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| title | FPGA PUF using programmable delay lines |
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| year | 2010 |
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| url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5711471 |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093