Difference between revisions of "Roy2008protecting"

From ACES

(Import from BibTeX)
 
m (Import from BibTeX)
Line 3: Line 3:
|abstract=Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.
|abstract=Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.
|pages=846 - 851
|pages=846 - 851
|month=
|year=2008
|booktitle=Design Automation Conference (DAC)
|booktitle=Design Automation Conference (DAC)
|title=Protecting bus-based hardware IP by secret sharing
|title=Protecting bus-based hardware IP by secret sharing
|entry=inproceedings
|entry=inproceedings
|date=2008-20-01
}}
}}

Revision as of 04:34, 4 September 2021

Roy2008protecting
entryinproceedings
address
annote
authorJ. Roy and F. Koushanfar and I. Markov
booktitleDesign Automation Conference (DAC)
chapter
edition
editor
howpublished
institution
journal
month
note
number
organization
pages846 - 851
publisher
school
series
titleProtecting bus-based hardware IP by secret sharing
type
volume
year2008
doi
issn
isbn
url
pdf


Icon-email.png
Email:
farinaz@ucsd.edu
Icon-addr.png
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Icon-addr.png
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093