Difference between revisions of "Koushanfar2011integrated"
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|abstract=<p>This paper presents an overview of hardware and Integrated Circuits (IC) metering methods. IC metering or hardware metering refers to tools, methodologies, and protocols that enable post-fabrication tracking of the ICs. Metering enables prevention and detection of overbuilt and counterfeit ICs in the dominant semiconductor contract-foundry model. Post-silicon identification and tagging of the individual ICs fabricated by the same mask is a precursor for metering: In passive metering, the ICs are specifically identified, either in terms of their functionality, or by other forms of unique identification. The identified ICs may be matched against their record in a pre-formed database that could reveal unregistered ICs or overbuilt ICs (in case of collisions). In active metering, not only the ICs are uniquely identified, but also parts of the chip\’s functionality can be only accessed, locked (disabled), or unlocked (enabled) by the designer and/or IP rights owners using a high level knowledge of the design not transferred to the foundry. We provide a systematic overview of the field, along with a taxonomy of available methods.</p> | |abstract=<p>This paper presents an overview of hardware and Integrated Circuits (IC) metering methods. IC metering or hardware metering refers to tools, methodologies, and protocols that enable post-fabrication tracking of the ICs. Metering enables prevention and detection of overbuilt and counterfeit ICs in the dominant semiconductor contract-foundry model. Post-silicon identification and tagging of the individual ICs fabricated by the same mask is a precursor for metering: In passive metering, the ICs are specifically identified, either in terms of their functionality, or by other forms of unique identification. The identified ICs may be matched against their record in a pre-formed database that could reveal unregistered ICs or overbuilt ICs (in case of collisions). In active metering, not only the ICs are uniquely identified, but also parts of the chip\’s functionality can be only accessed, locked (disabled), or unlocked (enabled) by the designer and/or IP rights owners using a high level knowledge of the design not transferred to the foundry. We provide a systematic overview of the field, along with a taxonomy of available methods.</p> | ||
|type=Invited Paper | |type=Invited Paper | ||
|month=5 | |||
|year=2011 | |||
|journal=GLSVLSI | |journal=GLSVLSI | ||
|title=Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview | |title=Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview | ||
|entry=conference | |entry=conference | ||
| | |pdf=Koushanfar2011integrated.pdf | ||
}} | }} | ||
Latest revision as of 02:53, 10 November 2021
| Koushanfar2011integrated | |
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| entry | conference |
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| author | Farinaz Koushanfar |
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| journal | GLSVLSI |
| month | 5 |
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| title | Integrated Circuits Metering for Piracy Protection and Digital Rights Management: An Overview |
| type | Invited Paper |
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| year | 2011 |
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| url | http://dl.acm.org/citation.cfm?id=1973110 |
| Koushanfar2011integrated.pdf | |
Email:
farinaz@ucsd.edu
farinaz@ucsd.edu
Address:
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Electrical & Computer Engineering
University of California, San Diego
9500 Gilman Drive, MC 0407
Jacobs Hall, Room 6401
La Jolla, CA 92093-0407
Lab Location: EBU1-2514
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093
University of California San Diego
9500 Gilman Dr, La Jolla, CA 92093