FPGA-based True Random Number Generation using Circuit Metastability with Adaptive Feedback Control

TitleFPGA-based True Random Number Generation using Circuit Metastability with Adaptive Feedback Control
Publication TypeConference Proceedings
Year of Publication2011
AuthorsMajzoobi, M., F. Koushanfar, and S. Devadas
Conference NameWorkshop on Cryptographic Hardware and Embedded Systems (CHES)
Date PublishedOctober, 2011
Abstract

The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effectiveness of our approach.

URLhttp://dl.acm.org/citation.cfm?id=2044931
AttachmentSize
FPGA-Random427.84 KB

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