Time-Bounded Authentication of FPGAs

TitleTime-Bounded Authentication of FPGAs
Publication TypeJournal Article
Year of Publication2011
AuthorsMajzoobi, M., and F. Koushanfar
JournalIEEE Transactions on Information Forensics and Security (TIFS)
Volume6
Issue3
Pagination1123-1135
Date Published3/2011
KeywordsDelay characterization, field-programmable gate arrays (FPGAs), Physically Unclonable Function (PUF), time-bounded authentication
Abstract

This paper introduces a novel technique to authenticate and identify field programmable gate arrays (FPGAs). The technique uses the reconfigurability feature of FPGAs to perform self-characterization and extract the unique timing of the FPGA building blocks over the space of possible inputs. The characterization circuit is then exploited for constructing a physically unclonable function (PUF). The PUF can accept different forms of challenges including pulse width, digital binary and placement challenges. The responses from the PUF are only verifiable by entities with access to the unique timing signature. However, the authentic device is the only entity who can respond within a given time constraint. The constraint is set by the gap between the speed of PUF evaluation on authentic hardware and simulation of its behavior. A suite of authentication protocols is introduced based on the time-bounded mechanism. We ensure that the responses are robust to fluctuations in operational conditions such as temperature and voltage variations by employing: (i) a linear calibration mechanism that adjusts the clock frequency by a feedback from on-chip temperature and voltage sensor readings, (ii) a differential PUF structure with real-valued responses that cancels out the common impact of variations on delays. Security against various attacks is discussed and a proof-of-concept implementation of signature extraction and authentication are demonstrated on Xilinx Virtex 5 FPGAs.

URLhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5737786
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Time-Bounded Authentication of FPGAs981.6 KB

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