GarbledCPU: A MIPS Processor for Secure Computation in Hardware

TitleGarbledCPU: A MIPS Processor for Secure Computation in Hardware
Publication TypeConference Paper
Year of Publication2016
AuthorsSonghori, E. M., S. Zeitouni, G. Dessouky, T. Schneider, A. - R. Sadeghi, and F. Koushanfar
Conference NameDesign Automation Conference
Date PublishedJune, 2016
KeywordsGarbled Circuit, Secure Function Evaluation
Abstract

We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao’s garbled circuit protocol in hardware. GarbledCPU provides three degrees of freedom for SFE which allow leveraging the trade-off between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.

URLdl.acm.org/citation.cfm?id=2898027
AttachmentSize
GarbledCPU.pdf334.15 KB

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