Hardware Trojan Horse Benchmark via Optimal Creation and Placement of Malicious Circuitry

TitleHardware Trojan Horse Benchmark via Optimal Creation and Placement of Malicious Circuitry
Publication TypeConference Paper
Year of Publication2012
AuthorsWei, S., K. Li, F. Koushanfar, and M. Potkonjak
Conference NameDesign Automation Conference (DAC)
Date PublishedJune, 2012
Keywordsbenchmark, gate-level characterization, Hardware Trojan, process variation
Abstract

This paper proposes Hardware Trojan (HT) placement techniques that yield challenging HT detection benchmarks. We develop three types of one-gate HT benchmarks based on switching power, leakage power, and delay measurements that are commonly used in HT detection. In particular, we employ an iterative searching algorithm to find rarely switching locations, an aging-based approach to create ultralow power HT, and a backtracking-based reconvergence identification method to determine the non-observable delay paths. The simulation results indicate that our HT attack benchmarks provide the most challenging representative test cases for the evaluation of side-channel based HT detection techniques.

URLhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6241495
Refereed DesignationRefereed
AttachmentSize
PDF310.96 KB

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